DDRop is a small, low-cost hardware interposer device that can make writes to a server’s memory disappear, causing the computer to read old data as if it were newly written. This trick has serious consequences for confidential computing technologies designed to protect sensitive workloads on shared cloud infrastructure. DDRop can interfere with protected virtual machines on Intel and AMD platforms and, on Intel TDX, even forge the security evidence used to prove that a virtual machine is trusted.

The missing guarantee: freshness

To handle large cloud workloads, the memory encryption in Intel TDX, Intel Scalable SGX, and AMD SEV-SNP keeps data confidential, but does not provide freshness. Without it, the processor can confirm that memory is encrypted; it cannot confirm that memory is current. Stale data still decrypts perfectly.
Why does a dropped write matter?
Think of encrypted memory as a locked notebook with no page numbers or dates. If an attacker stops a new line from being written, the old line remains. When you read it later, it still decrypts to valid text. The system has no way to tell that the latest update never arrived. DDRop uses this gap by silently discarding writes. A protected VM can then continue using old, attacker-chosen contents, while the encryption engine sees nothing wrong.

DDRop interferes with writes rather than trying to read encrypted data, so memory encryption does not stop the attack. It also uses interfaces that the hypervisor relies on to move protected memory, so the victim VM does not need to contain a software bug. On Intel TDX, we use the attack to put a confidential VM into debug mode and forge attestation reports.

A silent switch on the DDR5 bus

Earlier DDR5 interposers were passive and required bulky equipment. They also had to slow the memory bus to work with second-hand lab hardware, making the change easier to notice. DDRop is a compact board of analog switches that runs at native DDR5 speed and can be installed in minutes.

DDR5’s redesigned command bus makes the address-aliasing tricks used by earlier attacks impractical. DDRop instead interferes with the bus’s error handling. The interposer deliberately introduces a parity error and then suppresses the alert. The memory module discards the command, and the processor does not learn that the command was dropped. The write is gone.

All schematics, board files, and firmware are released as open source on our GitHub repository.

ComponentSupplierCost
Interposer PCB with stencilJLCPCB$45
Interposer electronic partsDigikey, LOTES$30
Controller board PCBJLCPCB$4
Controller electronic partsDigikey$40
Teensy 4.1 microcontrollerDigikey$40
Total$159

Bill of materials for a single interposer system (at a build quantity of 10). Excludes R&D and assembly labor.

DDRop in action: Breaking Intel TDX

Intel TDX isolates confidential virtual machines, called Trust Domains (TDs), from a potentially compromised host hypervisor. To prevent the privileged hypervisor from tampering with guest memory translations, TDX delegates address mappings to Secure Extended Page Tables (SEPT), which are encrypted in RAM under the respective TD’s key and managed exclusively by trusted firmware (the TDX module).

When the host allocates a new SEPT page (TDH.MEM.SEPT.ADD), the TDX module writes empty entries to securely initialize it. DDRop silently drops these writes, so the page keeps pre-crafted stale ciphertext that decrypts into malicious page-table entries. This primitive is 100% deterministic and lets an attacker-controlled TD remap its own memory onto any physical address in RAM. Under TDX’s default logical integrity (LI) mode, this allows the attacker to corrupt the ciphertext of other TDs and their control structures. Even TDX’s stronger cryptographic integrity (CI) mode would only prevent tampering across different key domains, still allowing an attacker to forge the attestation measurement of their own TD.

From dropped writes to arbitrary memory access
Controlling the secure page tables allows an adversary to read from and write to any physical address, including critical TDX metadata like debug status (LI) and launch measurement (LI + CI).

In production, Intel TDX strictly prevents the hypervisor from inspecting a TD's memory. A debug flag in the TD's attributes ensures the host cannot use the debug read/write API. However, the compromised SEPT mappings allow an attacker to corrupt these attributes, including the debug flag. Because this data is encrypted under a different key, it decrypts into pseudorandom noise, giving each attempt a 50% chance of setting the debug bit. Once active, the hypervisor dumps the victim's plaintext memory via the debug API and then cleanly restores the original captured ciphertext, leaving the victim running unaware with an unmodified attestation status.

To support remote attestation, the TDX module records the initial state of a TD in a launch measurement, which is signed on request so that a remote tenant can verify what was booted. Here the attacker targets a TD of their own: a rogue VM they launch and control, running whatever backdoor they like. Because this TD's control structure (TDCS) is encrypted under the attacker's own key, the injected SEPT entries give direct plaintext write access to it, allowing them to overwrite the launch measurement with that of a legitimate workload. When the rogue VM then requests an attestation report via TDG.MR.REPORT, the TDX module returns a valid report containing the forged measurement, so the backdoored VM passes remote attestation as if it were the trusted one.

Forged MRTD attestation measurement

Questions & Answers

DDRop is joint work by researchers at KU Leuven, ETH Zurich, Durham University, and Google:

For everyday laptops and phones, no: DDRop is a research attack aimed at confidential-computing servers in the cloud that run Intel TDX, Intel Scalable SGX, or AMD SEV-SNP on DDR5.

If you rely on those technologies to protect workloads from the cloud provider itself, this matters: DDRop shows that an attacker with brief physical access can undermine them. We disclosed everything to Intel and AMD in advance under coordinated disclosure.

Confidential computing is meant to protect sensitive data, even from the cloud provider. DDRop needs a brief, one-time visit to install the interposer. Besides that, DDRop assumes the standard TEE threat model, with the adversary controlling the OS/hypervisor and BIOS. Once the interposer is installed, the attack is carried out entirely in software. Possible ways to get that access include:

Data-center insiders
Rogue technicians, sysadmins, or contractors with server rack access.
Supply-chain tampering
Interposers planted, or modified modules swapped in, during transit or provisioning.
Compelled access
Physical hardware access compelled by law enforcement or governments.
DDRop needs physical access once
The interposer can be installed in minutes and runs at native DDR5 speeds. After installation, the attack is controlled in software.

It is a family of hardware features that let you run a workload in the cloud without having to trust the cloud provider. Popular platforms include Intel TDX and Scalable SGX, and AMD SEV-SNP. The hardware locks memory behind access control and encryption, so a physical adversary sees only scrambled data.

Standard Cloud VM Unrestricted Access
No Hardware Isolation
Standard Guest VM
Data stored unencrypted in host DRAM
Direct memory read / write / inspect access
Untrusted Host / Hypervisor
Full control over guest memory, page tables, and execution
Confidential VM Protected Data
Hardware Root of Trust / CPU Boundary
Confidential VM
Memory transparently encrypted by CPU engine
Direct access blocked by hardware memory encryption
Untrusted Host / Hypervisor
Manages physical server, but cannot read or alter CVM memory

Only partly. Vendors can make the attack harder by restricting the memory-management interfaces DDRop uses, checking that critical writes actually arrived, or looking for the interposer during boot. The paper discusses several defenses.

These measures do not add freshness to the memory-encryption hardware. The underlying problem is in hardware: today's scalable memory encryption does not keep track of whether a value is current. A lasting fix would require memory-encryption engines with integrity and freshness.

No. Memory encryption on TDX, SEV-SNP, and Scalable SGX protects confidentiality against someone reading the memory bus, but it lacks freshness and replay protection for this attack: it cannot distinguish a current value from an old one.

Encryption does not tell you whether data is current
Memory encryption protects the contents, but by itself it does not record whether a value is newer than the one it replaces. Without freshness counters or an integrity structure that detects stale data, an old ciphertext can still be accepted.

Physical attacks on encrypted cloud memory fall into two broad groups: attacks that listen to the memory bus and attacks that modify what happens on it. DDRop is the first active hardware interposer for current DDR5 servers.

Passive: listening to the bus observe traffic, then infer secrets via side channels
Membuster logo
2020
Snoops the unencrypted address of Intel Client SGX to learn access patterns with a high-end logic analyzer.
Passive DDR4 Client SGX Logic analyzer ~$170k
WireTap logo
2025
Uses a secondhand analyzer for ciphertext side-channel analysis on Scalable SGX platforms with downclocked DDR4 memory.
Passive DDR4 Scalable SGX Downclock Secondhand <$1k
TEE.fail logo
2025
Uses a secondhand analyzer for ciphertext side-channel analysis on TDX and SEV-SNP platforms with downclocked DDR5 memory.
Passive DDR5 TDX · SEV Downclock Secondhand <$1k
Active: tampering with the bus alter what the memory sees
BadRAM logo
2024
Makes a module lie about its size, which creates a hidden address alias. Patched with boot-time checks.
Active DDR4/5 SEV SPD chip <$10
Battering RAM logo
2025
Switches address aliasing on at runtime, which slips past boot-time checks. Works only for DDR4.
Active DDR4 SGX · SEV Runtime alias <$50
DDRop logo
2026
DDRop
Selectively drops writes to break scalable memory encryption on DDR5 lacking freshness.
Active DDR5 TDX · SGX · SEV Write drop <$200

The passive attacks (Membuster, WireTap, TEE.fail) observe traffic and use side channels to infer information. They use slower bus speeds to work with older lab equipment. DDRop is active and runs at native speed; the paper shows how it can copy plaintext between pages, alter page-table entries, and forge attestation. The defenses discussed in the paper can make the attack harder, but they do not add freshness to the memory-encryption hardware.

Vulnerable platforms bus-accessible memory without hardware freshness counters
Intel TDX
Evaluated on 5th Gen Xeon Scalable server. Affects both CVMs and the TDX Module, so we can force debug mode and forge attestation reports.
DDR5 AES-XTS Optional Integrity No Freshness
Intel Scalable SGX
Evaluated on 5th Gen Xeon scalable processor. The lack of freshness enables dropped writes to force stale data to victim enclaves.
DDR5 AES-XTS Optional Integrity No Freshness
AMD SEV-SNP
Evaluated on EPYC Turin. SEV encrypts memory but has no freshness to detect dropped writes. The relocation API lets us copy arbitrary victim pages.
DDR5 AES-XEX No Freshness
Immune architectures protected by hardware integrity trees
Intel Client SGX
Older desktop/laptop Intel Core CPUs use a hardware Merkle integrity tree with freshness counters, so the memory controller catches stale data.
DDR4 Merkle Tree Freshness Deprecated

We followed coordinated disclosure and shared our hardware, techniques, and proof-of-concept exploits with Intel and AMD ahead of time; we also informed Arm. These vendors have acknowledged our findings, but noted that physical attacks on DRAM are out of scope for their current products.

Intel has recently characterized research on hardware interposers as "out of scope but not out of mind" and indicated that it is considering next-generation memory-encryption schemes with stronger hardware protections. Research such as DDRop matters for understanding the fundamental limitations of today's technology and the attacker capabilities such attacks require, thereby informing the design of more robust memory-encryption schemes.

Following a coordinated disclosure on September 14, 2026, both vendors have issued a public security advisory: Intel advisory | AMD advisory.

01
DDR5 does not close the gap
DDR5's higher speeds and redesigned command protocol make bus tampering harder, but the paper shows that it is still practical at full speed.
02
Encryption needs freshness
Encryption alone does not prevent replay. If an attacker can drop writes and the hardware cannot detect stale data, integrity and attestation can be undermined.
03
Physical attacks are practical
Earlier attacks could require about $170,000 of lab equipment. The DDRop hardware costs less than $200 to build, according to the bill of materials above.

The full details are in the research paper, with hardware designs and proof-of-concept code on our GitHub repository.